This invention relates to a semiconductor device and, in particularly, to an internal power supply generating circuit for generating an internal power-supply voltage on the basis of an external power-supply voltage supplied from an outside and a semiconductor device comprising the same.
In resent year, high-speed and low power consumption are facilitated in semiconductor devices. For this purpose, the semiconductor device comprises an internal power supply generating circuit for generating an internal power-supply voltage VDL into which an external power-supply voltage supplied from outside is step-down and semiconductor device uses the internal power-supply voltage VDL as a high level of a small amplitude signal. For example, in semiconductor memory devices, the internal power-supply voltage VDL is generated as a voltage which is lower than the external power-supply voltage VEXT by a predetermined value. The internal power-supply voltage VDL is used as a voltage for writing data in a memory cell or a high level of a bit lines reading signal. Therefore, the internal power-supply voltage VDL is called an array power-supply voltage. Data transfer around a memory array is carried out at VDL/GND level serving as a power supply voltage having a small amplitude. In the manner which is described above, by making an signal amplitude of data small and by suppressing generation of noises, a high-speed data transfer has been allowed.
Although the high-speed of transfer rate is accomplished by making the signal amplitude of data small, it is disadvantageous in that an initial operation in reading-out/writing-in operations becomes slow. By resolving this problem, an overdrive reading-out method and an overdrive writing-in method are adopted in the semiconductor memory devices. The overdrive reading-out method makes a power-supply voltage applied to a sense amplifier high at an initial stage of the reading-out operation. On writing-in operation, if an input writing-in signal has a small amplitude, it is lacking in the ability to invert a signal between bit lines pair and a writing-in time becomes longer. For this purpose, the overdrive writing-in method supplies the sense amplifier with the external power-supply voltage VEXT at an initial stage of the writing-in operation. In the manner which is described above, inasmuch as a power-supply amplitude (VEXT/GND) larger than a signal amplitude (VDL/GND) is supplied to the sense amplifier, the overdrive reading-out method and the overdrive writing-in method are collectively called an overdrive method.
Various overdrive methods are already known. By way of example, a patent document 1 (Japanese Unexamined Patent Publication of Tokkai No. Hei 10-269,771 or JP-A 10-269771) discloses a technique idea for setting a suitable overdrive duration regardless of process variations. The patent document 1 discloses a semiconductor memory device comprising a sense amplifier for amplifying a signal produced between a complementary bit lines pair from a memory cell in synchronism with a sense amplifier drive signal, a common source lines pair for supplying the sense amplifier with a power supply voltage for operating it, overdrive transistors for overdriving the sense amplifier by extending a potential difference between the common source lines pair than a normal level only for a predetermined time internal from an operation start timing of the sense amplifier, and an overdrive pulse generating circuit for an overdrive pulse for controlling drive of the overdrive transistors. The overdrive pulse generating circuit includes a delay circuit for determining a pulse width of the overdrive pulse or the overdrive duration. In the patent document 1, by matching a gate length of a transistor constituting the delay circuit with a gate length of the overdrive transistors, process variations and manufacturing variations of an MOS transistor and are compensated. However, even in the same chip, there is a difference in design requirement between the overdrive transistors for use in the memory array and the transistor composing of the delay circuit for use in a peripheral control portion. To compensate the variations at the gate length as the same MOS transistor results in impairing design efficiency because the design requirement is generally matched with a reduced peripheral requirement. In addition, the overdrive method disclosed in the patent document 1 is deficient as a control method of the overdrive dependent on the external power-supply voltage.
Furthermore, a patent document 2 (Japanese Unexamined Patent Publication of Tokkai No. Hei 9-120,675 or JP-A 9-120675) and a patent document 3 (Japanese Unexamined Patent Publication of Tokkai No. Hei 10-242,815 or JP-A 10-242815) disclose a compensating method of the overdrive dependent on the external power-supply voltage.
The patent document 2 discloses a semiconductor integrated circuit which is capable of preventing an excessive overdrive even when a power supply voltage fed to a sense amplifier is high. The semiconductor integrated circuit disclosed in the patent document 2 includes a control circuit for supplying an operation power supply to a sense amplifier. The control circuit supplies, as the operation power supply, a power supply voltage (VDD) to the sense amplifier at an activation timing of the sense amplifier based on a first control signal which is initially activated, and then supplies, as the operation power supply, a step down voltage (VDL) having lower level than the power supply voltage to the sense amplifier based on a second control signal which is successively activated. The control circuit includes a delay circuit for determining an overdrive time interval between a time instant when the first control signal is activated and a time instant when the second control signal is activated. The control circuit includes an inverter circuit which is operable with the power supply voltage (VDD). The delay circuit has a delay time interval with negative dependency on the power supply voltage. However, in the patent document 2, a dependent relationship between the delay time interval and the power supply voltage (VDD) is restricted to characteristics of inverter elements constituting the inverter circuit.
The patent document 3 discloses a pulse generating circuit for use in a semiconductor device which is operable with an internal power-supply voltage (VINT) into which an external power-supply voltage (Vcc) is stepped down. The pulse generating circuit comprises a Vcc delay circuit, a VINT delay circuit, and a logical operation circuit. The Vcc delay circuit comprises a plurality of Vcc delay elements in a cascade connection fashion each of which consists of a CMOS inverter where a p-channel transistor has a source and a substrate both of which are supplied with the external power-supply voltage. The VINT delay circuit comprises a plurality of VINT delay elements in a cascade connection fashion each of which consists of a CMOS inverter where a p-channel transistor has a source supplied with the internal power-supply voltage and a substrate supplied with the external power-supply voltage. The logical operation circuit carries out logical operation on an output of the Vcc delay circuit and an output of the VINT delay circuit to generate a pulse. It will be assumed that the Vcc delay circuit comprises the Vcc delay elements consisting of 6-stage CMOS invertors while the VINT delay circuit comprises the VINT delay elements consisting of 2-stage CMOS invertors and the internal power-supply voltage VINT is equal to 2.5 volts. In this event, the Vcc delay circuit has a delay time interval which is equal to about 4 nanoseconds when the external power-supply voltage Vcc is equal to 3 volts and which is equal to about 3 nanoseconds when the external power-supply voltage Vcc is equal to 3.5 volts. On the other hand, the VINT delay circuit has a delay time interval which is equal to about 1.5 nanoseconds when the external power-supply voltage Vcc is equal to 3 volts and which is equal to about 1.8 nanoseconds when the external power-supply voltage Vcc is equal to 3.5 volts. The dependency is accelerated by a difference between the delay time interval of the Vcc delay circuit having a positive dependency on the external power-supply voltage Vcc and the delay time interval of the VINT delay circuit having a negative dependency on the external power-supply voltage Vcc.
Each of a patent document 4 (Japanese Unexamined Patent Publication of Tokkai No. 2000-058,785 or JP-A 2000-058785) and a patent document 5 (Japanese Unexamined Patent Publication of Tokkai No. 2001-266,573 or JP-A 2001-266573 which corresponds to U.S. Pat. No. 6,392,951) describes an overdrive on sensing a sense amplifier.
The patent document 4 discloses a dynamic type RAM which is capable of raising speed and of reducing a chip area. The dynamic type RAM disclosed in the patent document 4 comprises an N-channel type first power switch MOSFET, an N-channel type second power switch MOSFET, and an N-channel type third power switch MOSFET The N-channel type first power switch MOSFET supplies an over-drive voltage to a common source line. The N-channel type second power switch MOSFET supplies an internal high-voltage to the common source line. The N-channel type third power switch MOSFET supplies a ground voltage for a circuit to the common source line. The N-channel type first and third MOSFETs are distributed in an intersection region which the N-channel type second MOSFET is allocated apart in an indirect peripheral circuit on both or single side outside a memory array.
The patent document 5 discloses a semiconductor storage device in which drive of each sense means is not boosted unnecessarily even when a voltage generating means generating a voltage being higher than a predetermined driving voltage for a predetermined time interval from a sense start time instant is shared by a plurality of sense means. The semiconductor storage device disclosed in the patent document 6 includes sense amplifier rows for receiving a common sense amplifier drive voltage supplied by an internal voltage driver having a high current source mode. The semiconductor storage device may include banks of memory cells, row decoders, bank enable generation circuits, sense amplifier rows, sense amplifier drivers, sense amplifier control circuits, and internal voltage drivers. The internal voltage driver can include a high current source or high voltage mode, which can be received by a sense amplifier row during predetermined initial sense period. Other sense amplifier rows having already sensed data can be isolated from the internal voltage driver during the high current source or the high voltage source mode.
In general, in order to regulate the overdrive time interval, a delay element composed of a plurality of inverter elements is used. The delay element has a VDD dependency resolving an inverter characteristic and it is therefore difficult to make the delay element have the VDD dependency which is higher than that defined by the inverter characteristic. In addition, the overdrive time interval is regulated within an operational range of a ordinary product so that the VDD voltage satisfies a characteristic at a low side. Furthermore, in a case where a high-speed sensing characteristic is required, it generally demonstrates a propensity to make the overdrive time interval longer. Therefore, over-charging easily occurs at a high side of the VDD voltage. Conversely, when the overdrive time interval is regulated at the high side of the VDD voltage, it is short of the overdrive time interval at a low side of the VDD voltage, a high-speed operation is not good enough, and results in restricting a produce characteristic itself.
As an internal power supply generating circuit for generating an internal power-supply voltage on the basis of an external power-supply voltage supplied from outside, the following patent documents are known. A patent document 6 (Japanese Unexamined Patent Publication of Tokkai No. 2004-133,800 or JP-A 2004-133800 corresponding to U.S. Pat. No. 7,049,797) discloses a semiconductor integrated circuit device having a pair of voltage step-down power supply circuits for active and standby conditions. In the semiconductor integrated circuit device, a first reference voltage is formed by amplifying a fixed voltage formed in a fixed voltage generating circuit with an amplifying circuit which can adjust the voltage gain having a resistance circuit and a switch controlled with a first trimming switch setting signal. An internal step-down voltage, which the internal circuit is in the active condition, is outputted from a first output buffer, which is activated with a first control signal. A second reference voltage is formed by adjusting a combination of threshold voltages of MOSFETs and a switch controlled with a second trimming switch setting signal. An internal step-down voltage, when the internal circuit is in the standby condition, is outputted with a second output buffer, which is activated with a second control signal.
A patent document 7 (WO1998/058382 corresponding to U.S. Pat. No. 6,335,893) and a patent document 8 (Japanese Unexamined Patent Publication of Tokkai No. 2001-110,184 or JP-A2001-110184 corresponding to U.S. Pat. No. 6,366,506) disclose a power supply circuit which is capable of suppressing variations of a power supply voltage by stepping down an external power-supply voltage after stepping up the external power-supply voltage.
The patent document 7 discloses a semiconductor integrated circuit device comprising a first circuit block operating on a power supply voltage supplied through an external terminal and a second circuit block operating on an internal voltage generated by a power supply circuit. A voltage having an absolute value greater than that of the internal voltage is generated by a charge pump circuit. Variable impedance means is provided between the output voltage of the charge pump circuit and the internal voltage. A reference voltage and the internal voltage are compared by a differential amplifier circuit operating on the output voltage generated by the charge pump circuit. The variable impedance means is controlled such that those voltages agree with each other.
The patent document 8 discloses a semiconductor device which is capable of providing a supply means of an internal power-supply voltage being stable and flexible by solving a problem of supply of an operation power supply caused corresponding to drop of an external power-supply voltage externally supplied. The semiconductor device disclosed the patent document 8 comprises a first circuit block supplied with a first operating voltage, a second circuit block supplied with a second operating voltage, a voltage generating circuit for generating a third operating voltage in response to the first operating voltage, and a third circuit block supplied with the third operating voltage. Preferably, the third operating voltage is increased to a fourth operating voltage by a voltage-up converter, and then the fourth operating voltage is dropped to the third operating voltage by a voltage down-converter. Hence, a power supply operating internally stably in spite of use of a relatively fluctuating voltage can be provided even in the case of where a power-supply voltage is dropped. The patent document 8 discloses, in FIG. 5 thereof, a voltage down-converter comprising first and second voltage limiter circuits for generating reduced voltages corresponding to reference voltages by negative feedback operations respectively. Each of the first and the second voltage limiter circuit includes an operational amplifier constituted by a differential amplifier, and an output P-channel MOS with a gate controlled by the output of the differential amplifier. The first voltage limiter circuit converts the level of the reference voltage. The first voltage limiter circuit receives the reference voltage generated by a reference voltage generating circuit and generates a second reference voltage equal to a desired internal voltage by comparing the reference voltage with a tap voltage at a junction between resistors. The second reference voltage is a voltage substantially equal to a word line drive voltage. The first voltage limiter circuit is used because a voltage equal to the word line drive voltage can be hardly directly generated by the circuit for the reference voltage. If a voltage equal to the internal voltage can be generated directly from the reference voltage, the first voltage limiter circuit may be omitted so that the reference voltage generating circuit is directly connected to the second voltage limiter circuit as an internal voltage output buffer. The differential amplifiers and the output MOSs are provided to operate with a boosted voltage.
In addition, a patent document 9 (Japanese Unexamined Patent Publication of Tokkai No. 2000-306,382 or JP-A 2000-306382 corresponding to U.S. Pat. No. 6,339,344) discloses an input circuit which is capable of input levels having a large amplitude and a small amplitude. Specifically, the patent document 9 discloses a semiconductor integrated circuit device which realizes a low power consumption by supplying both a first-amplitude input signal and a second-amplitude input signal to a differential amplifier circuit. The first-amplitude input signal corresponds to a first operating voltage and a second operating voltage which are supplied respectively from a first MOSTFET and a second MOSFET. The second-amplitude input signal corresponds to a prescribed intermediate voltage between the first operating voltage and the second operating voltage. The patent document 9 discloses, in FIG. 2 thereof, an input circuit including a differential amplifier circuit. The differential amplifier circuit is constituted by connecting P-channel load MOSFETs in the form of a current mirror to the drain side of N-channel differential MOSFETs that are served with an input voltage and a reference voltage through the gages thereof, and by providing an N-channel current-source MOSFET on the common source side through an N-channel switching MOSFET. The current-source MOSFET is served with a ground potential of the circuit through the source thereof and is served with a constant voltage through the gate thereof. A P-channel switching MOSFET is provided between a power supply voltage and the common source of the P-channel load MOSFETs in the form of the current mirror.
In the manner which is described above, a power-supply voltage for an internal circuit is decreased while an overdrive method is used. This reason is necessary on manufacturing semiconductor devise. In this day and age, a device composed of the semiconductor device is moved their processed to finer design rules and is improved economy of scale for high integration and large capacity. A finer designed device has naturally a lowered withstand voltage. On the other hand, it is impossible to decrease a threshold voltage (Vt) of a transistor in proportion to the internal power-supply voltage in light of a leak characteristic of the transistor. For this purpose, a normal operation is activated by a low voltage and an initial operation only is activated by a high voltage using the overdrive method or a overcharging method. In the manner which is described above, a high-speed operation is realized by rising the voltage at the initial operation.
For example, a reading operation (a sensing operation) of memory cell data in a dynamic RAM (random access memory) uses an internal power-supply voltage VDL stepped down from an external power-supply voltage VEXT for a memory cell array. However, an initial sensing operation uses the external power-supply voltage VEXT by using the overdrive method. The overdrive methods are classified into an overcharging method of shorting the external power-supply voltage VEXT and the internal power-supply voltage VDL and an overdrive method of making an output of the internal power-supply voltage VDL the external power-supply voltage. In the manner which is described above, in the initial sensing operation, the external power-supply voltage due to the overdrive method is used. However, this inventor finds a problem in the overdrive methods to attain this invention. The problem lies in that the overdrive is carried out by the external power-supply voltage VEXT higher than the internal power-supply voltage in an initial operation duration for an sense amplifier.
Now, the description will proceed to the problem in the overdrive methods.
Data read out of the memory cell is sense-amplified as a minute difference voltage based on a reference voltage in the sense amplifier. In general, the reference voltage is substantially equal to a voltage HVCC which is half of the internal power-supply voltage VDL. In the initial operation for the sense amplifier, it is possible to carry out the sensing operation at a high speed by raising the internal power-supply voltage by using the overdrive method or the overcharging method. For instance, it will be presumed that the memory cell data is cell high (H) data higher than the voltage HVCC. In this event, an initial amplification is started by turning an N-channel transistor in the sense amplifier at a low voltage side on and successively a P-channel transistor in the sense amplifier at a high voltage side is turned on, and then the memory cell data is amplified. In order to carry out supply of electrical charges from the internal power-supply voltage VDL at a high speed because the P-channel transistor is turned on, the overdrive or the overcharging is carried out.
It is therefore possible to carry out high-speed operation for specs such as tRAS spec. In this event, an amount of electrical charges to be supplied remains unchanged although the read-out data is the cell high (H) data or is the cell low (L) data. This reason will be described as follow.
It will be assumed that a bit line where a selected cell is connected is called “TRUE(T) side bit line” while a bit line where the selected cell is not connected is called “NOT(N) side bit line.” When the memory cell data is the cell high (H) data, almost of the memory cells of 99% maintain the voltage VDL on be refreshed in a case where the memory cells are refreshed within a spec refresh interval. Accordingly, the cell potential does not change before and after refreshing and a potential between a bit line pair changes from the voltage HVCC to the voltage VDL alone. When the memory cell data is the cell high (H) data, the TRUE side bit line is charged from the voltage HVCC to the VDL. When the memory cell data is the cell low (L) data, a potential on the NOT side bit line changes from the voltage HVCC to the voltage VDL. That is, an amount of the electrical charges to be changed is the same but a difference occurs in a charging speed thereof.
At first, a capacitance to be changed is a sum of a bit line capacitance Cd and a cell capacitance Cs on the TURE side bit line when the memory cell data is the cell high (H) data. The capacitance to be changed is the bit line capacitance Cd only on the NOT side bit line when the memory cell data is the cell low (L) data. In addition, a voltage on staring the charging is equal to the voltage HVCC at the NOT side bit line (the cell L) and is equal to a voltage (HVCC+VR) at the TURE side bit line (the cell H), where VR represents a read-out potential from the memory cell. In a memory in recent times, the ratio of the bit line capacitance Cd to the cell capacitance Cs becomes smaller such as 4:1 to 3:1. Therefore, there is a difference of 20% to 25% in the capacitance to be changed between the TRUE side bit line (the cell H) and the NOT side bit line (the cell L) and a difference of 20% to 25% occurs in the voltages to be charged.
Due to this capacitance and this voltage difference, a difference occurs in the charging speed and a charging time interval up to a final voltage is different between the cell H and the cell L. In general, the charging P-channel transistor in early amplification has a drain-source voltage Vds of the NOT side higher than a drain-source voltage Vds of the TRUE side and has a large charging capacity. Inasmuch as the charging capacity and the capacitance to be charged are small, the potential on the NOT side bit line quickly overtakes a high level on the TURE side bit line. In the latter half of amplification, there is hardly a voltage difference between the voltage on the NOT side bit line and the voltage on the TRUE side bit line and there is no difference in the charging capacity of the transistor. Inasmuch as there is a capacity difference, the voltage on the NOT side bit line having a small capacity reaches to the voltage VDL earlier than the voltage on the TRUE side bit line. In the manner which is described above, although it becomes inescapable that there is a difference in the charging speed in dependent on H/L of the cell data, the semiconductor memory devices are designed so that there is no final voltage difference between both. In the description as follows, the description will be made on the assumption that the charging speed in the cell low (L) data is fast.
In the manner which is described above, although necessary electrical charges dependent on H/L of the cell data are equal to each other, there is a difference between the charging time intervals thereof. Accordingly, in the overdriving and the overcharging required in operation at the low voltage, control must be made so that an amount of the necessary electrical charges is not exceeded. However, under the current circumstances, a circuit configuration using the overdriving and the overcharging uses the external power-supply voltage VEXT. Therefore, a supply amount of the electrical charges due to the overdriving and the overcharging seriously has a dependence on a change in the external power-supply voltage VEXT.
It will be assumed that the external power-supply voltage VEXT is high. In this event, an excessive supply of electrical charges is carried out in the latter pattern and the internal power-supply voltage VDL does to back to an original level at a sensing end. Therefore, over step-up of the internal power-supply voltage VDL becomes issue. Conversely, it will be assumed that the external power-supply voltage VEXT is low. In this event, electrical charges to be supplied is less at the former pattern, sufficient overdriving is not carried out, and a sufficient restoring is not carried out in regard to the tRAS spec. In addition, if the electrical charges to be supplied is less at the letter pattern, turning-on of N-channel and P-channel transistors in the sense amplifier SA is late and unattainable tRCT characteristic and malfunction of the sense amplifier occur.
In addition, although the sensing is carried out in safety, the sense amplifier does not sufficiently carry out amplification on tRCD minimum spec of a high-speed sense characteristic. Although a column selection switch YSW is opened in this state, electrical charges to be supplied to an 10 data line is clearly smaller than that on the cell high (H) sensing. Therefore, a problem of data error sensing comes up in a data amplifier and it results in malfunctioning of the cell high (H) caused by the data amplifier. Accordingly, in the overcharging and the overcharging, it is necessary to have means for suitably controlling intensity thereof. However, in this day and age, with finer design rules, there are a lot of parameters outside a scaling rule, and it is difficult to carrying out sufficient control. Therefore, this invention is proposed in terms of power control means as further improvement means.
In the manner which will later be described in conjunction with FIGS. 1 through 4 in detail, a conventional internal power-supply generating circuit has a duration where the internal power-supply generating circuit cannot respond that is called a VDL dead band.
When there is the VDL dead band, the current supply is not carried out by an overdrive power supply and the internal power supply generating circuit and a high power-supply voltage (SAP) of the sense amplifier decreases heavily. As a result, the amplified voltage difference between the bit line pair reduces and a sense time interval becomes longer. Alternatively, a malfunction of the sense amplifier occurs. In the manner which is described above, when the overdrive is carried out at the output of the internal power supply generating circuit, the dead band where the internal power supply generating circuit does not operate occurs at a time when the overdrive comes to an end. It is therefore disadvantageous in that the access time interval becomes longer or the malfunction of the sense amplifier occurs. Accordingly, it is necessary for the internal power supply generating circuit used in the overdrive method to have structure where the dead band does not occur or to have means for suitably controlling the dead band. However, the above-mentioned prior art patent documents 1 to 9 neither describe nor understand a problem for the dead band in the internal power supply generating circuit that is founded by the present inventor. Accordingly, inasmuch as the problem is not understood, the above-mentioned prior art patent documents 1 to 9 never teach technique for resolving the problem.